This invention generally relates to treating the surface of semiconductor wafers intended for use in microelectronics, optics and optoelectronics applications. A particular example described herein concerns an SOI (Silicon On Insulator) type wafer. In particular, the invention concerns a method for minimizing slip line faults on the semiconductor surface that includes heating the wafer to a first higher temperature, a pause at the first temperature to stabilize the wafer, and further heating the wafer during a predetermined time period to a target higher temperature. The semiconductor wafers relating to the invention are formed via a layer transfer technique, which means that at least one layer (corresponding to all or a part of the wafer) has been transferred from a source substrate onto a support.
The term “rapid annealing” means annealing that takes the wafers to very high temperatures (about 1100° C. or more), in a very short time (a few tens of seconds). This type of annealing is commonly referred to as Rapid Thermal Annealing (RTA). RTA allows the surface of the wafers to be smoothed.
FIG. 1 is a graph that illustrates how RTA is currently practiced, with a curve that shows how the temperature T increases over time t. The graph illustrates that the RTA process includes two ramps where the temperature rises, which takes the wafers subject to the RTA from room temperature (RT) to a high, end-of-annealing temperature T2 in a very short time. For example, RT can range from between about 20° C. and 500° C., and T2 can be about 1200° C.
FIG. 1 shows that the RTA process comprises two rectilinear ramps. The first ramp takes the wafer from room temperature RT to a temperature T1 of about 750° C., which is followed by a halt or pause of about 10 seconds at this same temperature. This first ramp and the pause initiates heating, and permits initiation of the rise to a follow-up temperature of the wafer (the follow-up temperature is measured by a pyrometer which is capable of determining the temperature of the wafer. But the temperature of the wafer only becomes “readable” by the pyrometer after a certain temperature threshold is reached, which depends on the material of the wafer—in the case of a wafer of silicon the temperature threshold is about 400° C.). The first ramp and the pause also permits the temperature to be stabilized (which is the particular role of the halt). After the pause, the RTA process continues with a second ramp having a slope of about 50° C. per second followed by a halt or pause of about 30 seconds. This second ramp is an important active phase of the RTA process.
It has been observed that such conventional RTA processes cause faults to appear in the wafers, particularly in the case of silicon wafers (SOI for example). These faults are known as slip lines and result from the thermal constraints that the wafer is subject to during RTA. These thermal constraints result from the very steep ramps or steep temperature increases, as well as because of the final halt or pause at a very high temperature. Therefore, more or less slip lines will be observed on a wafer subjected to a conventional RTA process depending on the thermal budget applied to the wafer.
Slip lines are likely to appear over the entire surface of the wafer, and notably on the elements that support the wafer inside the annealing oven. Such slip lines are detrimental.